1. Technical Field
The present disclosure relates to computer systems and, more particularly, to ATA compatible data transfer systems and methods of data transfer in ATA compatible data transfer systems.
2. Discussion of Related Art
Advanced Technology Attachment or AT Attachment (ATA) is a standard mass storage device bus interface used to connect devices such as hard drives, floppy disk drives, CD-ROM and DVD-ROM drives to personal computers. Technical Committee T13 for the InterNationai Committee on Information Technology Standards (INCITS) is responsible for all interface standards relating to the ATA storage interface. Several versions of the ATA interface have been defined. Generally, ATA devices store data in 512-byte blocks called sectors. Logical block addressing (LBA) mode is a means set forth by the ATA standards to allow for the linear addressing of sectors.
Intelligent/Integrated Drive Electronics (IDE) is a general term for drives with built-in disk controllers and a popular term used for ATA disk drives. Although IDE refers to a general technology, whereas ATA refers to a specific specification, the term IDE is often used as a synonym for ATA because ATA devices are also IDE devices. The IDE interface is based on the IBM PC Industry Standard Architecture (ISA) 16-bit bus standard, but it is also used in computers that use other bus standards. Enhanced IDE (EIDE) is a newer version of the IDE interface that supports data transfer rates that are about four times faster than the original IDE interface. EIDE uses logical block addressing, which allows for hard disk capacities over 528 MB. EIDE makes use of DMA (Direct Memory Access) channels and can address up to four ATA devices.
One method of transferring data over the ATA bus is through the use of programmed I/O (PIO). In PIO, the system CPU is responsible for executing the instructions that transfer the data in contiguous blocks of data that are multiples of 512 bytes between the system and the drive. The ATA Read Sectors and Write Sectors generate interrupt signals to the CPU for reading and writing each sector. This approach can place heavy demands on the CPU whenever the drive needs to transfer data, particularly multimedia data, to or from memory.
With the advent of faster host systems and devices, PIO has been expanded to include new operating modes. Each of the PIO modes, numbered zero through four, is faster than the one before. The PIO modes are defined in terms of their cycle time, representing how many nanoseconds it takes for each transfer to occur. The maximum transfer rate is the reciprocal of the cycle times doubled because the ATA interface is two bytes (16 bits) wide.
FIG. 1 is a block diagram showing a conventional PIO system. Referring to FIG. 1, the conventional PIO system 10 includes a host 1, interface device 2, input/output (I/O) interface 11, and external storage 3. The host 1 includes a system controller 101, such as a CPU, and system memory 102. The system controller 101 sets a PIO mode (speed) and outputs a system address to host controller 121.
The interface device 2 is composed of a device host 12, a device controller 13, and a device register 14. The device host 12 includes a device controller 121 and an ATA controller 123. The device controller 13, which is coupled between the device host 12 and the device register 14, is coupled to external storage 3. The device register 14 may include a command block register and control block register. The device controller 13 accesses control data from/to the device register 14 and outputs to the ATA controller 123. The system controller 101 communicates with device controller 13 through the host controller 121 and ATA controller 123 to assert the various address, select, read/write request and enable signals (e.g., CS0n, CS1n, DIORn and DA) for access to the device controller 13 and external storage 3. In the conventional PIO system, the system controller 101 is Interrupted each time an external device, such as a hard disk drive, requires data transfer. In operations requiring extensive access to the external device, such as storage or transfer of large files to/from a hard disk, the processing resources of the system controller/CPU can be depleted. The processing load worsens when more external devices are added to the system.
As multimedia components such as DVDP (Digital Video Development Platform) drive, set-top box, personal video recorder (PVR), digital television (DTV), MP3 player, or portable multimedia player (PMP), e.g., with a Microdrive, etc. attain widespread consumer appeal and usage, system designers look to add more and more external devices to computer systems. An IDE extension protocol was developed called the AT Attachment Packet Interface or ATAPI for these devices. ATAPI facilitates external devices like optical, tape and removable storage drives to plug into the standard IDE cable used by IDE/ATA hard disks, and be configured as master or slave, etc. like a hard disk. The ATAPI protocol is similar but not identical to the standard ATA (ATA-2, etc.) command set used by hard disks. The load/burden placed on the processing resource is similar because ATAPI is also interrupt driven.
Direct Memory Access (DMA) is a transfer protocol where the data is transferred directly between drive and memory without using the CPU to perform the transaction, in contrast to PIO. There are two types of DMA: third-party DMA and first-party or bus mastering DMA. Third-party DMA uses the DMA controller built into the system to perform bus arbitration for use of the system bus to transfer the data. (The “third party” is the DMA controller.) First-party DMA allows the hard disk and system memory to work without relying on the system's DMA controller, or requiring any support from the CPU.
Over the last few years, faster data transfer rates have been achieved, using a standard commonly called “Ultra ATA”, in systems equipped with the Ultra DMA protocol. Before Ultra DMA, one transfer of data occurred on each clock cycle, triggered by the rising edge of the interface clock or “strobe”. Ultra DMA uses double-edge clocking. Double-edge clocking allows data to be transferred on each edge of the rising strobe, doubling the data-transfer rate without increasing the fundamental frequency of signaling on the bus. Additionally, Ultra DMA uses non-interlocked signaling. With non-interlocked signaling, the clock signal is generated by the source and sent with the data, whereas in typical synchronous clocking designs, data is transmitted from the source and clocked at the receiver using a local clock signal. Ultra DMA modes 0, 1, 2, 3 and 4 have maximum transfer rates of 16.7, 25, 33.3, 44.4 and 66.6 MB, respectively. Even using double-edge clocking, transfer rates above 33 MB/sec exceed the capabilities of the original 40-conductor standard IDE cable. To use Ultra DMA modes over 2, an 80-conductor IDE cable is required.
A need therefore exists for ATA compatible data transfer systems and methods of data transfer that facilitate increased peripheral loading yet relieves the processing load placed on the system CPU.